(a) Field of the Invention
The present invention relates to a synchronization system and method thereof in digital communication. More specifically, the present invention relates to a synchronization system and method thereof in digital communication for easy hardware implementation and reduction of effects caused by channels or noise, and thereby obtaining better synchronization performance.
(b) Description of the Related Art
In order to normally transmit and receive data between a transmitter and a receiver in a digital communication system, successful synchronizing is required. Synchronization transmission methods in digital communication systems are classified into frequency synchronization, symbol synchronization, and frame synchronization.
In particular, the symbol synchronization transmission method is divided into two methods according to symbol types. First, when a zero-crossing occurs in a single symbol period, the symbol synchronization transmission method that transmits clock timing signals through the symbol type uses the zero-crossing to adjust symbol synchronization.
In this symbol synchronization transmission method, a waveform is referred to as a return-to-zero (RZ), and it has poor frequency performance.
Next, the symbol synchronization transmission method using a non-return-to-zero (NRZ) waveform has good frequency performance since it does not directly load the timing signals on the symbols, but it requires an additional synchronization circuit.
A receiving end of the digital communication system performs the symbol synchronization through an early-late gate method that compares values output by an early integrator and a late integrator having a marginal time difference within a single symbol period to perform a symbol synchronization process.
Since the early-late gate method performs the symbol synchronization using closed loop control, it is difficult to select control parameters, and since the performance or stability of the loop depends upon the parameter values, it is difficult to implement the method.
To compensate for these problems, U.S. Pat. Nos. 4,794,624 and 5,241,545 disclose methods for using an oversampling method instead of the closed loop control method.
First, the method for clock synchronization of a signal receiver of the U.S. Pat. No. 4,794,624 relates to a digital communication system's receiving end for obtaining the symbol synchronization for demodulating digital signals.
That is, the above-disclosed patent comprises an analog/digital converter, a symbol sign estimator, a subtractor, a square-law unit, an integrator, and a comparator. A receiving end receives band-limited signals from a transmitting end and oversamples a single symbol period into a plurality of subsamples, calculates distribution values at each sample point of the symbol, and the comparator then determines an optimized synchronization point.
In this case, since the symbol sign estimator estimates a symbol sign of a signal previously received for symbol synchronization, the performance of the system may be lowered because of noise.
Also, since a multiplier used for the square-law unit uses much time in the clock signal synchronization method of the signal receiver, it is not appropriate for use in a high-fast communication system.
U.S. Pat. No. 5,241,545, entitled “Apparatus and method for receiving a time-varying signal using multiple sampling points” relates to symbol synchronization acquisition and maintenance in a digital packet communication system.
For this, the patent comprises an analog/digital converter, a data buffer, and a correlator, and finds correlation values of as many as the number of those oversampled for each symbol interval between a receiving signal and a reference signal, and selects the maximum correlation value as the synchronization point.
The above-described apparatus and method periodically repeats the above process to maintain the synchronization in a single packet, but it has a problem in that its hardware becomes complex because of the buffer or the correlator, and the data transmission rate becomes lowered because of overloads at the point where time-varying of a channel is less.
Also, in order to find the correlation value, a random signal is to be used as a synchronization code, but since the random signal has bad fading channel characteristics, an initial correlation performance may be lowered.
Therefore, since the apparatus and method uses a specific synchronization code to find the correlation value, the apparatus and method lowers performance of the symbol synchronization in a frequency-selective fading channel.
Since the above US patents use a square-law unit, a subtractor, a buffer, or a correlator in a symbol synchronization block, its corresponding hardware configuration becomes complex, and since their processing speed is limited, they are not appropriate for high-speed data transmission.